Semiconducting carbon nanotubes can conduct exceptionally high currents for their nanoscale diameter (i.e., diameters of from about 1 nanometer (nm) to about 2 nm). However, in spite of carbon nanotubes' high current density (up to 109 Amps per square centimeter (A/cm2)), their small size still limits carbon nanotubes to carrying tens of microamps each.
In the context of using carbon nanotubes to replace silicon as an active channel material for next-generation transistors, the achievable current from a carbon nanotubes-based device must be comparable to silicon technology (about 1 milliamp per micrometer (mA/μm)). Difficulty in controllably fabricating closely packed, parallel (aligned) carbon nanotube arrays has kept the achievable current around 0.02 mA/μm. See, for example, K. Ryu, et al., “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes,” Nano Lett., vol. 9, pp. 189-197 (2009).
Reports suggest that in order to obtain 1 mA/μm from aligned carbon nanotubes, the pitch from nanotube to nanotube would have to be near 10 nm, which is an order of magnitude smaller than the best reproducibly obtained density to date. See, for example, A. Raychowdhury, et al., “Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits,” IEEE TED, vol. 56, pp. 383-392 (2009). Another alternative is the use of random carbon nanotube networks known as thin-film transistors, but the current in these systems becomes even more limited by percolation and/or poor carbon nanotube-metal contacts from bundling. See, for example, Q. Cao, et al., “Medium-Scale Carbon Nanotube Thin-Film Integrated Circuits on Flexible Plastic Substrates,” Nature, vol. 454, pp. 495-502 (2008).
Therefore, techniques for increasing the current carrying capacity of carbon nanotube-based devices would be desirable.